Competition 2024
Competition: Hardware Implementation

Arrhythmia Analysis Accelerator : A-Cube

We propose the A-Cube design methodology to create medical decision support on the edge. The design and implementation of an atrial fibrillation detector hardware core was selected as a proof-of-concept study. To facilitate the required atrial fibrillation functionality, we adopted an established AI model, based on Long Short-Term Memory (LSTM) technology for hardware implementation. The adaptation was done by varying design parameters such as data window and the number of LSTM units. We found that a data window of 40 beats and 20 LSTM units are sufficient to achieve a classification accuracy of 99.02%. We are confident that the A-Cube methodology can be used to implement this model in hardware. Doing so, will create a low power and low latency atrial fibrillation monitoring solution which has the potential to extend the observation duration while being convenient for patients.

 

Project Milestones

  1. Milestone #1

    Target Date

    Implement and test the Soclab encryption example in the ZCU104 FPGA board.

  2. Milestone #2

    Target Date

    Implement an atrial fibrillation detection model in the ZCU104 FPGA board.

  3. Milestone #3

    Target Date

    Analyse the model performance based on different signal length and algorithm complexity.

  4. Milestone #4

    Target Date

    Analyse the model performance based on different quantisation levels.

  5. Milestone #5

    Target Date

    Select a suitable implementation candidate to server as atrial fibrillation detection core.

  6. Milestone #6

    Target Date

    Simulate (RTL) the selected atrial fibrillation detection core.

  7. Milestone #7

    Target Date

    Implement an AHB bus interface for the selected atrial fibrillation detection core.

  8. Milestone #8

    Target Date

    Integrate Soclab and the selected atrial fibrillation detection core.

  9. Milestone #9

    Target Date

    Simulate the integration results.

  10. Milestone #10

    Target Date

    Implement the integration results in the ZCU104 FPGA board.

  11. Milestone #11

    Target Date

    Test the hardware on the ZCU104 FPGA board.

  12. Milestone #12

    Target Date

  13. Milestone #13

    Target Date

Comments

It was good to hear you confirm the Architectural design pattern for data movement within your proposed SoC. It was interesting talking through the various options:

  1. Using the processor to Poll status registers for results. Using the processor to periodically inspect status registers associated with the processing of the external data for both data handling and obtaining results can consume unnecessary processor cycles and may not allow the processor to enter low power modes. Polling might be needed during initiation sequences before the main operating cycles of the SoC are established.
  2. Using an Interrupt driven approach where by your custom hardware raises an interrupt request signal on the processor when it requires service. The processor then accesses the status registers only when required and avoids the overhead of period polling. The processor is still active in managing all the data transfer in the system. 
  3. Using a separate Direct Memory Access (DMA) controller as an Initiator (Master) for data movement transactions. Interrupts on the processor are raised only when additional processing needs to be undertaken. 

Given the low data bandwidth requirements for you specific project you felt the DMA approach was not needed. A simple interrupt architectural design pattern with a mapping of registers within your custom hardware into the address space of the processor and accessible from the main system bus was I recall your proposed design. This will be a combination of data, status and result registers.

It will be good to see how this develops.

Atrial Fibrillation (AF) is a common heart rhythm disorder which increases the stroke risk fivefold . It is estimated that AF prevalence in the UK is around 1% of the general population and increases to 10% within the older population. AF is diagnosed by analysing the electrocardiogram (ECG) of the human heart. Figure 1 shows an ECG signal before and during an AF episode.   This analysis can be done manually, which is labour intensive or with artificial intelligence (AI) models.  Currently the AI models are executed in cloud servers and the data must travel from the point of measurement to that server over a network. Communicating the data requires network connectivity and energy expenditure associated with accessing the network. Furthermore, communication channels pose data safety and security issues. Moreover, a setup procedure is needed for transferring patient data to the cloud server. These systemic issues limit the observation duration of measurement equipment, such as patch sensors for heart rate capturing. The reduced observation duration will reduce the number of observable AF episodes which has a negative impact on AF diagnosis.  

You are able to build nanoSoC with the DMA removed. The two nanoSoC designs taped out recently had either the DMA 230 or the DMA 350. Aba and the team are developing an accelerator core with micro DMA engines within their accelerator design. This allows them to generate similar firmware for their FPGA implementation as their ASIC implementation. They have been varying the nanoSoC project to build without the  DMA 230 or DMA 350 IP but containing their addressing within the accelerator expansion region. 

We propose the A-Cube design methodology to create medical decision support on the edge. The design and implementation of an atrial fibrillation detector hardware core was selected as a proof-of-concept study. To facilitate the required atrial fibrillation functionality, we adopted an established AI model, based on Long Short-Term Memory (LSTM) technology for hardware implementation. The adaptation was done by varying design parameters such as data window and the number of LSTM units. We found that a data window of 40 beats and 20 LSTM units are sufficient to achieve a classification accuracy of 99.02%. We are confident that the A-Cube methodology can be used to implement this model in hardware. Doing so, will create a low power and low latency atrial fibrillation monitoring solution which has the potential to extend the observation duration while being convenient for patients.

Add new comment

To post a comment on this article, please log in to your account. New users can create an account.

Project Creator
rami hariri

researcher student at anglia ruskin university
Research area: AI

Related Articles
2024 IEEE 37th International System-on-Chip Conference

Submitted on

Actions

Log-in to Join the Team