Arrhythmia Analysis Accelerator : A-Cube
We propose the A-Cube design methodology to create medical decision support on the edge. The design and implementation of an atrial fibrillation detector hardware core was selected as a proof-of-concept study. To facilitate the required atrial fibrillation functionality, we adopted an established AI model, based on Long Short-Term Memory (LSTM) technology for hardware implementation. The adaptation was done by varying design parameters such as data window and the number of LSTM units. We found that a data window of 40 beats and 20 LSTM units are sufficient to achieve a classification accuracy of 99.02%. We are confident that the A-Cube methodology can be used to implement this model in hardware. Doing so, will create a low power and low latency atrial fibrillation monitoring solution which has the potential to extend the observation duration while being convenient for patients.
Project Milestones
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Milestone #1Target Date
Implement and test the Soclab encryption example in the ZCU104 FPGA board.
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Milestone #2Target Date
Implement an atrial fibrillation detection model in the ZCU104 FPGA board.
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Milestone #3Target Date
Analyse the model performance based on different signal length and algorithm complexity.
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Milestone #4Target Date
Analyse the model performance based on different quantisation levels.
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Milestone #5Target Date
Select a suitable implementation candidate to server as atrial fibrillation detection core.
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Milestone #6Target Date
Simulate (RTL) the selected atrial fibrillation detection core.
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Milestone #7Target Date
Implement an AHB bus interface for the selected atrial fibrillation detection core.
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Milestone #8Target Date
Integrate Soclab and the selected atrial fibrillation detection core.
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Milestone #9Target Date
Simulate the integration results.
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Milestone #10Target Date
Implement the integration results in the ZCU104 FPGA board.
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Milestone #11Target Date
Test the hardware on the ZCU104 FPGA board.
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Milestone #12Target Date
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Milestone #13Target Date
Comments
Updates to milestones (end of May 2024)
Hi,
It would be good to get an update on your milestones at the end of the month.
I think you have been working on the interface Atrial Fibrillation Detection Accelerator core to main Nanosoc. As I understand things, you were considering the need for a DMA for data transfer. If you do not use a DMA the processor will have to initiate all transfer of data between your sensor input and your custom accelerator.
Let us know where you have got to?
John.
Nanosoc Configuration
Hi Rami,
We've just updated the way you can configure nanosoc, to hopefully make it more easy for people to make changes to the overall configuration without having to change multiple files. If you pull the latest changes you should see a nanosoc.config in the nanosoc_tech directory
If you leave the options blank, they will not be included and if you write a yes (or really any text after) then it will be included. There is also a section to edit the paths to arm IP
You should now not have to make any edits to flists (apart from to include your accelerator) or to any of the makefiles
Let me know how it goes
Daniel
Architectural design pattern for data movement within the SoC
It was good to hear you confirm the Architectural design pattern for data movement within your proposed SoC. It was interesting talking through the various options:
Given the low data bandwidth requirements for you specific project you felt the DMA approach was not needed. A simple interrupt architectural design pattern with a mapping of registers within your custom hardware into the address space of the processor and accessible from the main system bus was I recall your proposed design. This will be a combination of data, status and result registers.
It will be good to see how this develops.
Introduction
Atrial Fibrillation (AF) is a common heart rhythm disorder which increases the stroke risk fivefold . It is estimated that AF prevalence in the UK is around 1% of the general population and increases to 10% within the older population. AF is diagnosed by analysing the electrocardiogram (ECG) of the human heart. Figure 1 shows an ECG signal before and during an AF episode. This analysis can be done manually, which is labour intensive or with artificial intelligence (AI) models. Currently the AI models are executed in cloud servers and the data must travel from the point of measurement to that server over a network. Communicating the data requires network connectivity and energy expenditure associated with accessing the network. Furthermore, communication channels pose data safety and security issues. Moreover, a setup procedure is needed for transferring patient data to the cloud server. These systemic issues limit the observation duration of measurement equipment, such as patch sensors for heart rate capturing. The reduced observation duration will reduce the number of observable AF episodes which has a negative impact on AF diagnosis.
Generating the nanoSoC ASIC within HLS4ML
You are able to build nanoSoC with the DMA removed. The two nanoSoC designs taped out recently had either the DMA 230 or the DMA 350. Aba and the team are developing an accelerator core with micro DMA engines within their accelerator design. This allows them to generate similar firmware for their FPGA implementation as their ASIC implementation. They have been varying the nanoSoC project to build without the DMA 230 or DMA 350 IP but containing their addressing within the accelerator expansion region.
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