Introduction

Precision timekeeping is a foundational service in any distributed system. Whether synchronising Ethernet frames to a PTP grandmaster, timestamping die-to-die packet exchanges between chiplets, or scheduling time-critical hardware events, the system needs a clock that is accurate, capturable at multiple points simultaneously, and adjustable by both hardware servo loops and software without stopping.

The NanoSoC Ethernet Subsystem provides an AHB based TCP/IP Offload Engine that provides a SoC system with external Ethernet connectivity without adding the network handling workload to the main SoC processor.

To utilise chiplets for small M-class microcontroller based systems there is a need to extend the range of the AHB standard on-chip bus interconnect. This 'Tidelink' project extends the planned AXI Chiplet controller to support AHB transactions across chiplets.

This project demonstrates running the lwIP UDP/IP stack on a MicroBlaze soft processor within an XIlinx PYNQ-Z2 FPGA to create a simple embedded Ethernet communications subsystem. The design integrates a custom Ethernet PHY interface and AXI EthernetLite MAC to enable basic networking functionality. An lwIP echo server runs on the MicroBlaze, while the Zynq Processing System hosts a UART bridge application for host communication. The project is being used to undertake design exploration for soft-core processors in FPGA logic to implement and verify lightweight networking stacks.