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Research Area
Formal modelling
Role
Researcher
Name
Research Area
Formal System Development
Role
Lecturer
Research Area
Cyber-physical systems
Role
Senior Research Fellow
Research Area
UML-B
Role
Dean of the Faculty of Engineering and Physical Sciences
Research Area
Advanced Packaging
Role
Cleanroom Process Integration Engineer
Research Area
Security of Hardware
Role
National Teaching Fellow
Research Area
Microwaves, Antennas, RFID/RFIC, Packaging
Role
UK IC Research Fellow and Proleptic Lecturer

Known Good Dies

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Copyright 2022 © Arm and University of Southampton | All Rights Reserved

COILS-C1 65nm SoC with M0 cores in 3D stack

Low-cost 3D die stacking using near-field wireless communication.

This two-tier SoC, fabricated using a TSMC 65nm process, incorporates two Arm Cortex M0 CPU cores in addition to a wireless vertical AHB lite bus for inter-layer power and data transfer. The wireless AHB-Lite bus consists…

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SoClabs

nanoSoC 2023/4

The first tape out of the nanoSoC Cortex M0 based SoC Reference Design. This reference design provides a simple microcontroller system appropriate to host and support the development and evaluation of research IP blocks or subsystems. It supports seamless transition from FPGA to physical silicon …

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Copyright 2022 © Arm and University of Southampton | All Rights Reserved

Pipistrelle-4 65nm low power multi-project SoC

Pipistrelle-4, is the latest in a series SoCs for demonstrating multiple student projects in low-energy systems. Various circuit/system ideas from multiple researcher focusing on energy and performance with optimised SRAM bitcell and low-area overhead energy-efficient flip-flops.

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University of Southampton

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United Kingdom of Great Britain and Northern Ireland (the)
Members icon Members 39
Projects icon Projects 35
Articles icon Articles 7
Contributor since icon Contributor since: Wed, 06/30/2021 - 14:50
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Projects

Collaborative
Active Project
SDIO Controller Verification
Integration of an open source SD Card interface submodule into megaSoC with a clear verification strategy to know it works, end-to-end, to provide a persistent storage mechanism.
Reference Design
Active Project
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DRAM Controller integration in megaSoC

To enable full operating system support in megaSoC, a substantial amount of memory is required to accommodate the complexity of modern Linux-based software stacks, including the kernel, drivers, middleware, and user-space applications. Linux environments, unlike lightweight bare-metal systems such as nanoSoC, demand not only larger memory footprints but also consistent access to high-bandwidth memory to maintain performance across multitasking workloads. The most common approach is to incorporate external DRAM, which offers the necessary capacity and throughput.

Collaborative
Active Project
PTP Hardware Clock: Sub-Nanosecond Timekeeping for Chiplet Systems
Introduction

Precision timekeeping is a foundational service in any distributed system. Whether synchronising Ethernet frames to a PTP grandmaster, timestamping die-to-die packet exchanges between chiplets, or scheduling time-critical hardware events, the system needs a clock that is accurate, capturable at multiple points simultaneously, and adjustable by both hardware servo loops and software without stopping.

Collaborative
Active Project
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NanoSoC Ethernet Subsystem
The NanoSoC Ethernet Subsystem provides an AHB based TCP/IP Offload Engine that provides a SoC system with external Ethernet connectivity without adding the network handling workload to the main SoC processor.