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Research Area
Formal modelling
Role
Researcher
Name
Research Area
Formal System Development
Role
Lecturer
Research Area
Cyber-physical systems
Role
Senior Research Fellow
Research Area
UML-B
Role
Dean of the Faculty of Engineering and Physical Sciences
Research Area
Advanced Packaging
Role
Cleanroom Process Integration Engineer
Research Area
Security of Hardware
Role
National Teaching Fellow
Research Area
Microwaves, Antennas, RFID/RFIC, Packaging
Role
UK IC Research Fellow and Proleptic Lecturer

Known Good Dies

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

COILS-C1 65nm SoC with M0 cores in 3D stack

Low-cost 3D die stacking using near-field wireless communication.

This two-tier SoC, fabricated using a TSMC 65nm process, incorporates two Arm Cortex M0 CPU cores in addition to a wireless vertical AHB lite bus for inter-layer power and data transfer. The wireless AHB-Lite bus consists…

SoClabs

nanoSoC 2023/4

The first tape out of the nanoSoC Cortex M0 based SoC Reference Design. This reference design provides a simple microcontroller system appropriate to host and support the development and evaluation of research IP blocks or subsystems. It supports seamless transition from FPGA to physical silicon …

Copyright 2022 © Arm and University of Southampton | All Rights Reserved

Pipistrelle-4 65nm low power multi-project SoC

Pipistrelle-4, is the latest in a series SoCs for demonstrating multiple student projects in low-energy systems. Various circuit/system ideas from multiple researcher focusing on energy and performance with optimised SRAM bitcell and low-area overhead energy-efficient flip-flops.

P…

University of Southampton

Country
United Kingdom of Great Britain and Northern Ireland (the)
Members 34
Projects 23
Articles 7
Contributor since: Wed, 06/30/2021 - 14:50
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Projects

Collaborative
Active Project

Indonesia Collaborative SoC Platform

This program is dedicated to the development of a System on Chip (SoC) platform, specifically designed to support learning and research activities within Indonesian academic institutions. The platform serves as an educational and research tool for students, lecturers, and researchers to gain hands-on experience in digital chip design.

Collaborative
Active Project
AHB Qspi architectural design
dwn @ soclabs

AHB eXcecute in Place (XiP) QSPI

The instruction memory in the first tape out of nanosoc was implemented using SRAM. The benefit was the read bandwidth from this memory was very fast, the downside was on a power-on-reset, all the code was erased as SRAM is volatile memory. An alternative use of non-volatile memory would benefit applications where  deployment of the ASIC does not allow, or simply time is not available for programming the SRAM after every power up. 

Reference Design
Active Project
soclabs nanosoc microcontroller framework - 2024
soclabs

nanosoc - baseline Cortex-M0 microcontroller SoC (2024 update)
A small SoC development framework to support easy integration and evaluation of academic developed research hardware such as a custom accelerators or signal processing sub-systems.
Reference Design
Active Project
Imrpoved power domain structure for nanosoc
dwn @ soclabs

nanoSoC Low Power Implementation

As part of plans for continued development of nanoSoC one area that requires improvement is the power structure of system. The first iteration of nanoSoC contained 2 power domains: the accelerator domain and the remainder of the SoC. Both power domains were connected to external pins to allow connection to separate external voltage regulators and power measurement ICs, as implemented in the first version of the nanoSoC testboard.