CMOS image sensors (CIS) play a crucial role in the imaging industry. CIS produces low-quality images in low-light conditions. Single Photon Avalanche Diode (SPAD) is a device used for low-light imaging because of its ability to detect single photons of light. To detect a single light photon, SPAD is biased above its breakdown voltage (Gieger mode). When the photon hits the active area during Geiger mode, a significant reverse current (avalanche current) is observed.

Efficiency in hardware is vital as neural network models become more complex to tackle challenging problems, and optimizing ML hardware architectures has become a crucial research area. Scientists around the world, such as particle physicists at CERN need to accelerate their ML models in FPGA or custom ASICs for various applications including compressing the gigantic amount of data generated by the detectors at Large Hadron Collider (LHC).

Neural networks have enabled state-of-the-art approaches to achieve impressive results on many image processing and analysis tasks. However, while gigapixel images are gaining ground in domains like satellite imaging and digital pathology, feeding neural networks directly with these ultra-high-resolution images is still computationally challenging. With a growing number of high-resolution computer vision applications being proposed, the need for an efficient and powerful AI acceleration system targeting gigapixel images rises.

Modern Convolutional Neural Networks (CNNs) are known to be computationally and memory costly owing to the deep structure that is constantly growing. A reconfigurable design is crucial in tackling this difficulty since neural network requirements are always evolving. The suggested architecture is adaptable to the needs of the neural network.