Hi,

Thanks for the latest milestones. I see "the on-chip storage is 4MB or 8MB to cater the needs of neural network computations". I was interested in how this compares to the ChipKit tape out.

That project had the following die:

With 4MB SRAM and a SoC architecture of:

Hi,

In Draft this has a type of 'Reference Design' but I think it is more likely either a competition entry or a normal collaboration style project that does not have a fixed time window like a competition entry. Would you like to adjust the type of the project and submit it?

We look forward to collaborating with you.

John.

Hi,

I think this project description doesn't fit with the current aims of SoC Labs and the contest. I think you will need to reconsider it if you want to continue. 

Please can you add details of the potential collaboration?

Thank you.

Can you please update the project or perhaps it is time to retire it?

Thank you for submitting this project, it looks very interesting and I look forward to hearing more about it. 

If you need any help, just add a reply here and we will see what we can do to help.

We look forward to hearing from you.

This item on Cortex M voice solutions might be useful in determining the system requirements and some of the decisions needed in establishing the SoC Architecture.

Breaking down the processing to core parts such as inputs and data requirements of the ML processing to identify system resource requirements.

The data transfers for input and model through the system. 

There are some approximate figures,  "minimum of 300KB for model storage (assuming 
100s of domain specific utterances)". Do you have any views on model sizes and through put?

We look forward to hearing from you.

On chip memory is a critical aspect of SoC area/cost. A recent paper on Optimizing the Deployment of Tiny Transformers on Low-Power MCUs considered the issue of high memory footprint of intermediate results and frequent data marshaling. The paper discusses the issue of memory constraints and techniques for data movement such as the use of Direct Memory Access.

If you can provide some idea of data sizes and movement requirements it will help. 

It would be great to get an update on where you have got to with this project.

We look forward to hearing from you.

Have you made any changes to the last system architecture you proposed?