I am just letting you know that we have some news in terms of the local activities we are working on the help SoC Design activities in Canada.

We have a new collaboration project (here) working with Semiconductor Education Alliance partners to help develop a range of local activities in Canada.  

You might want to join this project and hear about what is being developed?

"Ted (Kezhi) is investigating a custom wrapper file for the ADC, drawing from https://soclabs.org/project/adc-integration-nanosoc"

Please reach out and ask for any help you need. An easy way is to simply add a comment on the ADC integration project and Daniel should respond. Asking questions in this way not only helps you but also other people. We are very keen to get people to collaborate on IP blocks and also design flow and environment issues.

Look forward to hearing from you.

Here is an interesting paper on a model to determine FPGA resources for multi-layer neural networks. Part of their conclusions is “LSTM turned out to be very demanding on FPGA computing resources”.  Do you have a view on the LSTM implementation you will need for this application? 

I am not sure if this is of any help but perhaps you can take a look at this call

Applied global health research: stage one – UKRI