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High Capacity Memory Subsystem Development

Introduction

This project aims to design and implement a high capacity memory subsystem for A series CPU based SoCs. 

Team

Name
Sandeepan Roy
Research Area
Computer architecture, Machine Learning, Accelerator Design, Architecture Verification
Role
Independent Researcher
Name
Soumya
Research Area
SOC WITH AI
Role
Student
Profile picture for user Dhanaji_Pawar
Name
Dhanaji Pawar
Research Area
Accelerator Design , Architecture Verification,Computer architecture
Role
Design and Verification engineer

Comments

Hi All, 
Could you please use this link to join the introductory meeting this friday at 3pm UK time (BST)
https://teams.microsoft.com/l/meetup-join/19%3ameeting_NzJmOWMzZjQtMTYxNi00NTA3LTlhMTQtMjMwNDY4N2NhMDQw%40thread.v2/0?context=%7b%22Tid%22%3a%224a5378f9-29f4-4d3e-be89-669d03ada9d8%22%2c%22Oid%22%3a%22da03259c-2f3e-4038-96bb-de5e01994a6c%22%7d

Hi Folk, 

  You can check out this website to get some insights into the LPDDR Memory Architecture. The exact spec is not yet finalized yet and will let you know the details once I have it (ETA : 1 Week). 

Thanks, & Regards 

Srimanth Tenneti 

Link: https://www.systemverilog.io/design/lpddr5-tutorial-physical-structure/

Hello Everyone,  

We are planning to organize a meeting sometime next week to kickoff the project and introduce ourselves. Could each one of you post your areas of interest (related to the project) for us to get an understanding of the team we have here ?

Also kindly let us know your availability (Time and Time Zone) for a meeting on Friday next week.

 

Thanks & Regards 

-Srimanth Tenneti 

 

Template : 

Name :

Areas of Interest : Micro-Architecture/RTL Design/STA/Physical Design/Verification/ ...

Hi, 

   I am here to ask if the JEDEC specification for DDR4 SDRAM is accessible to any member in this group. Based on my understanding of DDR4 SDRAM,  the design is based on DDR Controller and DDR PHY. If the specification could be accessed, then the design could be learnt in-depth.

Here is the link for DDR4 specification: https://www.jedec.org/standards-documents/docs/jesd79-4a

Hi,

We have just finished our 2nd video call for the project. We did not record it. Not everyone has signed up on the slack channel which will be a location for frequent communication. We will make a regular update to the project so that everyone can keep aware of the weekly drum beat. Srimanth said we would share the meeting summary so hopefully we will draft that up and share it later.

Srimanth discussed his rough block diagram of the DDR Command Generation module. 

An initial design decomposition focusing on the signal interchange was felt to be a good start to allow people to engage. 

Various blocks need fleshing out and we need to assign people have a first look and then we can see why the blocks are misaligned. 

We will continue to meet weekly and try and move things forward. Look out for the more details meeting summary. 

John. 

 

 

 

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Project Creator
Srimanth Tenneti

Researcher at University of Cincinnati
Research area: Machine Learning | SoC Design

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